Many computing platforms, particularly portable and other low power devices, incorporate a system on a chip (SoC) as a primary processor. These SoC's are configured to support a platform's programming model to ensure that software functions properly. Some SoC's that follow personal computer (PC)-based standards implement program ordering semantics defined according to a Peripheral Component Interconnect Express (PCI Express™ (PCIe™)) Specification, e.g., as described in the PCI Express™ Specification Base Specification version 2.0 (published Jan. 17, 2007), typically using hardware.
One notable aspect of the ordering architecture is that downstream memory mapped input output (MMIO) writes from a host agent to an input/output (IO) agent travel the same path as read completion data returning to the IO agent from memory. This path is referred to as the outbound path, since it travels away from a root complex of the SoC. Per PCIe™ rules, a memory read completion to the IO agent cannot bypass any prior agent MMIO write that has been posted onto the same virtual channel. Essentially then, the resulting traffic on this outbound path is not controllable, which can lead to starvation and misallocation issues.